1. Field of the Invention
The present invention relates to solid-state image sensors. More particularly, the present invention relates to a frame store imager that converts and stores the image information digitally in each pixel.
2. The Prior Art
Frame store imagers are known in the prior art. Thus far, frame store imaging schemes have usually been based on storage of the image signal level on an intra-pixel capacitor as an analog voltage.
While analog pixel sensors have been used successfully, they have several problems. First, leakage during readout limits the signal-to-noise ratio and also the maximum array size. Transistor scaling will decrease the size of transistor devices but at the expense of increased noise of numerous kinds. It is presently believed that pixel size will be limited to about 3 um by optical properties such as diffraction and that Moore""s law will continue to apply, thus making inevitable the use of more transistors per pixel.
There have been several frame store imaging schemes that convert the analog image signal to a digital signal within the pixel. U.S. Pat. No. 5,461,425 to Fowler et al. and U.S. Pat. No. 5,801,657 to Fowler et al. are examples of such schemes.
According to a first aspect of the present invention, a digital storage pixel sensor according to the present invention includes a photodiode coupled to a reset potential through a reset transistor that reverse biases the photodiode. The photodiode is coupled to a storage capacitance through a transfer transistor. The storage capacitor is coupled to a first input of a voltage comparator. A second input of the voltage comparator is coupled to the analog ramp voltage output of a ramp generator. The ramp generator starts an n-bit counter at the beginning of each voltage ramp. As presently preferred, the n-bit counter is configured as a Gray code counter.
After an exposure interval, the transfer switch turns off to temporarily store the analog signal at the first input to the comparator. When the ramp voltage passes the voltage established by charge accumulation in the pixel sensor, the comparator changes state. The comparator output writes the present count of the counter into an n-bit dynamic random access memory (DRAM) word disposed in the imager. To read the memory contents, the counter outputs are disabled and a read signal is supplied to the n-bit DRAM word. The counter lines then serve as output column lines for the imager""s DRAM.
According to a second aspect of the present invention, an array of digital storage pixel sensors is provided. According to a presently preferred embodiment, each imager in the array is served by the same n-bit counter and analog ramp voltage and the n-bit column line outputs are common to all digital storage pixel sensors in individual columns of the array and also serve as column output lines for all of the DRAM words in individual columns of the array. DRAM words in individual rows of the array are selected for output by row-enable signals provided to the digital storage pixel sensors in individual rows of the array.